Resumen

CHACON-RODRIGUEZ, A.; MARTIN-PIRCHIO, F. N.; JULIAN, P.  y  MANDOLESI, P. S.. A Verilog HDL digital architecture for delay calculation. Lat. Am. appl. res. [online]. 2007, vol.37, n.1, pp.41-45. ISSN 0327-0793.

A method for the calculation of the delay between two digital signals with central frequencies in the range [20, 300] Hz is presented. The method performs a delay calculation in order to determine the bearing angle of a sound source. Computing accuracy is tested against a previous implementation of the Cross Correlation Derivative method. A Verilog RTL model of the method has been tested on a Xilinx® FPGA in order to evaluate the real performance of the method. Simulations of an ASIC design on a standard CMOS technology predict a power saving of about 25 times per delay stage over previous implementations.

Palabras clave : Verilog; FPGA; Low Power; Digital CMOS VLSI.

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