Resumo

ARNONE, L.; GAYOSO, C.; GONZALEZ, C.  e  CASTINEIRA, J.. Sum-subtract fixed point LDPC decoder. Lat. Am. appl. res. [online]. 2007, vol.37, n.1, pp.17-20. ISSN 0327-0793.

In this paper a low complexity logarithmic decoder for a LDPC code is presented. The performance of this decoding algorithm is similar to the original decoding algorithm's, introduced by D. J. C. MacKay and R. M. Neal. It is a simplified algorithm that can be easily implemented on programmable logic technology such as FPGA devices because of its use of only additions and subtractions, avoiding the use of quotients and products, and of float point arithmetic. The algorithm yields a very low complexity programmable logic implementation of a LDPC decoder with an excellent BER performance.

Palavras-chave : Low Density Parity Check Codes; Decoding; BER Performance; Look-Up Tables.

        · texto em Inglês     · Inglês ( pdf )